1. Field of the Invention
This invention relates to digital data communication and, more particularly, to reliable communication of digital data between different clock domains.
2. Description of the Related Art
New techniques to ensure the reliability of the communication of digital data have become necessary as the speed of communication links has increased. Particularly within computer memory systems, a reference clock may accompany parallel digital data so as to provide a mechanism for determining the appropriate time to sample the data. However, it is often the case that multiple clock domains are established within a given communications system due to the difficulties involved in distributing a single clock throughout a large system. Although the clocks of each individual clock domain may have the same frequency, it is to be expected that the phase relationship between any two clocks in different domains will vary depending on changes in voltages and temperature between the domains over time. Jitter in the phase offset between a transmitting clock and a receiving clock tends to move the sampling point away from the ideal point in the received data signal, resulting in poor timing margins and/or a higher bit-error-rate (BER). The higher the speed at which a communications link is clocked, the more significant the effects of phase jitter become. Therefore, it is desirable to have a mechanism to determine when to sample the data at the receiver while maintaining a robust time margin thereby reducing the impact of phase changes between clock domains and enabling higher communication speeds.
In addition to the above considerations, the use of serial communication links to convey digital data within computer memory subsystems has become commonplace. For example, banks of fully buffered dual inline memory modules (FB-DIMMs), which may be used to provide increased memory capacity in computer systems, are commonly connected to each other via a serial ring bus. Each serial link in the ring bus may be equipped with a serializer/deserializer (SerDes) device whose serialization function converts parallel data from within the FB-DIMM to serial data for transmission on the ring bus. A typical SerDes includes a shift register for this purpose. The clock that clocks the shift register may be part of a different clock domain than the clock that clocks the parallel data within the FB-DIMM. It is desirable for the shift register to be loaded at a time that is near the midpoint of the parallel data clock to provide for adequate timing margin. It is also desirable for the shift register to be loaded at a time after the last bit of a parallel data sample has been shifted out so as to preserve frame alignment in the serial data. Accordingly, what is needed is a technique for simultaneously satisfying the constraints of sampling parallel data with adequate time margin and synchronization of the shift register's load time and serial clock.